74 search results - page 2 / 15 » Future Execution: A Hardware Prefetching Technique for Chip ... |
MICRO
2009
IEEE
14 years 12 days ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
ASPLOS
2011
ACM
12 years 9 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
DATE
2008
IEEE
14 years 7 days ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
HPCA
2004
IEEE
14 years 6 months ago
2004
IEEE
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...