13 search results - page 1 / 3 » GPE: A New Representation for VLSI Floorplan Problem |
ICCD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper, we propose a new representation of VLSI floorplan and building block problem. The representation is the generalization of Polish expression [1]. By proposing a new ...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
––In this paper, a corner block list — a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...