232 search results - page 2 / 47 » Generalised Resource Model for Parallel Instruction Scheduli... |
HPCA
2004
IEEE
14 years 6 months ago
2004
IEEE
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
IJAIT
2008
13 years 5 months ago
2008
Instruction scheduling is one of the most important steps for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction sch...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
DAC
1995
ACM
13 years 9 months ago
1995
ACM
Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade–off between flexibility and cost. However, existing code generation metho...
IPPS
2000
IEEE
13 years 10 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...