DAC 1995 - PDF Preprint Papers

DAC 1995 Design Automation Conference

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DAC
1995
ACM

230views Computer Architecture» more DAC 1995»

The Case for Design Using the World Wide Web

13 years 8 months ago

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— Most information and services required today by designers will soon become available as documents distributed in a wide area hypermedia network. New integration services are re...

Mário J. Silva, Randy H. Katz

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Id	Views	Title	Status

1	230	The Case for Design Using the World Wide Web	claim
2	211	Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems	claim
3	183	Code Optimization Techniques for Embedded DSP Microprocessors	claim
4	180	A Survey of Optimization Techniques Targeting Low Power VLSI Circuits	claim
5	178	Automatic Clock Abstraction from Sequential Circuits	claim
6	174	Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores	claim
7	172	Performance Analysis of Embedded Software Using Implicit Path Enumeration	claim
8	159	A Transformation-Based Approach for Storage Optimization	claim
9	155	Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs	claim
10	144	Register Allocation and Binding for Low Power	claim
11	143	On the Bounded-Skew Clock and Steiner Routing Problems	claim
12	140	Automatic Layout Synthesis of Leaf Cells	claim
13	139	Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs	claim
14	135	Parallel Logic Simulation of VLSI Systems	claim
15	135	Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits	claim
16	130	Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing	claim
17	129	Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead	claim
18	129	Rephasing: A Transformation Technique for the Manipulation of Timing Constraints	claim
19	127	Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization	claim
20	125	New Performance-Driven FPGA Routing Algorithms	claim
21	125	Incorporating Design Schedule Management into a Flow Management System	claim
22	125	Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods	claim
23	124	Requirements-Based Design Evaluation	claim
24	124	DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm	claim
25	124	Symbolic Modeling and Evaluation of Data Paths	claim
26	124	Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits	claim
27	124	A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis	claim
28	123	Efficient Power Estimation for Highly Correlated Input Streams	claim
29	122	Power Estimation in Sequential Circuits	claim
30	120	Fast Identification of Robust Dependent Path Delay Faults	claim
31	117	The Elmore Delay as a Bound for RC Trees with Generalized Input Signals	claim
32	116	An Efficient Algorithm for Local Don't Care Sets Calculation	claim
33	111	Hierarchical Optimization of Asynchronous Circuits	claim
34	110	Timing Driven Placement for Large Standard Cell Circuits	claim
35	108	Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems	claim
36	108	A Methodology for HW-SW Codesign in ATM	claim
37	107	Performance-Driven Partitioning Using a Replication Graph Approach	claim
38	106	The Validity of Retiming Sequential Circuits	claim
39	105	A General Method for Compiling Event-Driven Simulations	claim
40	104	Synthesis of Software Programs for Embedded Control Applications	claim
41	97	On Test Set Preservation of Retimed Circuits	claim
42	93	Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits	claim
43	91	Logic Synthesis for Engineering Change	claim
44	89	A Fresh Look at Retiming Via Clock Skew Optimization	claim
45	87	Delayed Frontal Solution for Finite-Element Based Resistance Extraction	claim

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