Sciweavers

44 search results - page 8 / 9
» Generation of Executable Representation for Processor Simula...
Sort
View
CASES
2005
ACM
13 years 7 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
13 years 11 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
APN
2008
Springer
13 years 7 months ago
Modeling and Analysis of Security Protocols Using Role Based Specifications and Petri Nets
Abstract. In this paper, we introduce a framework composed of a syntax and its compositional Petri net semantics, for the specification and verification of properties (like authent...
Roland Bouroulet, Raymond R. Devillers, Hanna Klau...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
13 years 11 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
ICDCS
2011
IEEE
12 years 5 months ago
Starlink: Runtime Interoperability between Heterogeneous Middleware Protocols
—Interoperability remains a challenging and growing problem within distributed systems. A range of heterogeneous network and middleware protocols which cannot interact with one a...
Yérom-David Bromberg, Paul Grace, Laurent R...