68 search results - page 13 / 14 » Generation of compact test sets with high defect coverage |
SP
2008
IEEE
14 years 20 hour ago
2008
IEEE
Attacks often exploit memory errors to gain control over the execution of vulnerable programs. These attacks remain a serious problem despite previous research on techniques to pr...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the me...
VC
2008
13 years 5 months ago
2008
Modeling is a severe bottleneck for computer graphics applications. Manual modeling is time consuming and fails to capture the complexity of real world scenes. Automated modeling b...
DATE
2009
IEEE
14 years 12 days ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
TCAD
1998
13 years 5 months ago
1998
—New methods for fault-effect propagation and state justification that use finite-state-machine sequences are proposed for sequential circuit test generation. Distinguishing se...