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CODES
2008
IEEE
13 years 6 months ago
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
13 years 11 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
AOSD
2009
ACM
14 years 18 days ago
Dependent advice: a general approach to optimizing history-based aspects
Many aspects for runtime monitoring are history-based: they contain pieces of advice that execute conditionally, based on the observed execution history. History-based aspects are...
Eric Bodden, Feng Chen, Grigore Rosu
WWW
2004
ACM
14 years 6 months ago
VersaTutor: architecture for a constraint-based intelligent tutor generator
Intelligent tutoring systems have demonstrated their utility in a variety of domains. However, they are notoriously resource intensive to build. We report here on the development ...
Viswanathan Kodaganallur, Rob R. Weitz, David Rose...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
13 years 11 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan