591 search results - page 1 / 119 » Global delay optimization using structural choices |
FPGA
2010
ACM
14 years 2 months ago
2010
ACM
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
HPCA
2002
IEEE
14 years 6 months ago
2002
IEEE
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
DATE
2007
IEEE
13 years 12 months ago
2007
IEEE
Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal e ects impact a...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...