Sciweavers

19 search results - page 1 / 4
» Guaranteeing Hits to Improve the Efficiency of a Small Instr...
Sort
View
MICRO
2007
IEEE
73views Hardware» more  MICRO 2007»
13 years 11 months ago
Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache
Stephen Hines, David B. Whalley, Gary S. Tyson
LCTRTS
2009
Springer
14 years 2 days ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
13 years 10 months ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane
SAC
2008
ACM
13 years 4 months ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
Roberto Giorgi, Paolo Bennati
INFOCOM
2002
IEEE
13 years 10 months ago
Using the Small-World Model to Improve Freenet Performance
– Efficient data retrieval in a peer-to-peer system like Freenet is a challenging problem. In this paper we study the impact of cache replacement policy on the performance of Fre...
Hui Zhang 0002, Ashish Goel, Ramesh Govindan