9 search results - page 2 / 2 » Guaranteeing performance yield in high-level synthesis |
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
ASPDAC
2009
ACM
13 years 12 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...