112 search results - page 22 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
CF
2009
ACM
14 years 8 days ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
ERSA
2007
13 years 7 months ago
2007
The emergence of high-density reconfigurable hardware devices gives scientists and engineers an option to accelerating their numerical computing applications on low-cost but power...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
CEE
2007
13 years 5 months ago
2007
It is a challenge to implement large word length public-key algorithms on embedded systems. Examples are smartcards, RF-ID tags and mobile terminals. This paper presents a HW/SW c...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
This paper presents the Customisable Modular Platform (CMP) approach. The aim is to accelerate FPGA application developraising the level of abstraction and facilitating design reus...