25 search results - page 3 / 5 » Hardware Implementation of Temporal Nonmonotonic Logics |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—A large part of a modern SOC’s debug complexity resides in the interaction between the main system components. ion-level debug moves the abstraction level of the debug process...
ATVA
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. The bounded synthesis problem is to construct an implementation that satisfies a given temporal specification and a given bound on the number of states. We present a so...
ICLP
1997
Springer
13 years 9 months ago
1997
Springer
Kowalski and Sergot’s Event Calculus (EC) is a simple temporal formalism that, given a set of event occurrences, derives the maximal validity intervals (MVIs) over which propert...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...