45 search results - page 1 / 9 » Hardware Performance Simulations of Round 2 Advanced Encrypt... |
AES
2000
Springer
13 years 9 months ago
2000
Springer
CATA
2010
13 years 5 months ago
2010
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round...
CTRSA
2001
Springer
13 years 10 months ago
2001
Springer
The results of fast implementations of all five AES final candidates using Virtex Xilinx Field Programmable Gate Arrays are presented and analyzed. Performance of several alternati...
FPGA
2000
ACM
13 years 9 months ago
2000
ACM
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the ...