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TC
2011
13 years 22 days ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ACSD
2010
IEEE
255views Hardware» more  ACSD 2010»
13 years 3 months ago
From POOSL to UPPAAL: Transformation and Quantitative Analysis
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control syst...
Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jac...
SENSYS
2004
ACM
13 years 11 months ago
TinySec: a link layer security architecture for wireless sensor networks
We introduce TinySec, the first fully-implemented link layer security architecture for wireless sensor networks. In our design, we leverage recent lessons learned from design vul...
Chris Karlof, Naveen Sastry, David Wagner
HPDC
2008
IEEE
14 years 7 days ago
The performance of bags-of-tasks in large-scale distributed systems
Ever more scientists are employing large-scale distributed systems such as grids for their computational work, instead of tightly coupled high-performance computing systems. Howev...
Alexandru Iosup, Omer Ozan Sonmez, Shanny Anoep, D...
IPPS
2003
IEEE
13 years 11 months ago
An Executable Analytical Performance Evaluation Approach for Early Performance Prediction
Percolation has recently been proposed as a key component of an advanced program execution model for future generation high-end machines featuring adaptive data/code transformatio...
Adeline Jacquet, Vincent Janot, Clement Leung, Gua...