230 search results - page 1 / 46 » Hardware Support for Control Transfers in Code Caches |
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
Many dynamic optimization and/or binary translation systems hold optimized/translated superblocks in a code cache. Conventional code caching systems suffer from overheads when con...
IJHPCA
2006
13 years 4 months ago
2006
In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
IEEEPACT
2009
IEEE
2009
IEEE
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
13 years 11 months ago
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
IISWC
2008
IEEE
13 years 11 months ago
2008
IEEE
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...