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ECBS
2006
IEEE
126views Hardware» more  ECBS 2006»
13 years 12 months ago
Experiments and Investigations for the Personal High Performance Computing (PHPC) built on top of the 64-bit processing and clus
The motivation and objective for this paper is to demonstrate “Personal High Performance Computing (PHPC)”, which requires only a smaller number of computers, resources and sp...
Victor Chang
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
13 years 11 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
DAC
2005
ACM
14 years 6 months ago
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trad
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
Andrey V. Zykov, Elias Mizan, Margarida F. Jacome,...
CIT
2006
Springer
13 years 9 months ago
A High Performance ASIC for Cellular Automata (CA) Applications
CA are useful tools in modeling and simulation. However, the more complex a CA is, the longer it takes to run in typical environments. A dedicated CA machine solves this problem by...
Cheryl A. Kincaid, Saraju P. Mohanty, Armin R. Mik...
DAC
2005
ACM
14 years 6 months ago
High performance encryption cores for 3G networks
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
René Cumplido, Tomás Balderas-Contre...