Sciweavers

23 search results - page 3 / 5
» Hardware synchronization for embedded multi-core processors
Sort
View
DATE
2004
IEEE
173views Hardware» more  DATE 2004»
13 years 9 months ago
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee
ASYNC
2005
IEEE
112views Hardware» more  ASYNC 2005»
13 years 11 months ago
Request-Driven GALS Technique for Wireless Communication System
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
Milos Krstic, Eckhard Grass, Christian Stahl
ASPLOS
1996
ACM
13 years 9 months ago
Synchronization and Communication in the T3E Multiprocessor
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...
Steven L. Scott
SBCCI
2009
ACM
188views VLSI» more  SBCCI 2009»
13 years 12 months ago
Low-power inter-core communication through cache partitioning in embedded multiprocessors
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
Chenjie Yu, Xiangrong Zhou, Peter Petrov
ACSD
2006
IEEE
105views Hardware» more  ACSD 2006»
13 years 11 months ago
Throughput Analysis of Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for...
Amir Hossein Ghamarian, Marc Geilen, Sander Stuijk...