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» Hardware-Assisted Design for Fast Packet Forwarding in Paral...
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ANCS
2005
ACM
13 years 10 months ago
SSA: a power and memory efficient scheme to multi-match packet classification
New network applications like intrusion detection systems and packet-level accounting require multi-match packet classification, where all matching filters need to be reported. Te...
Fang Yu, T. V. Lakshman, Martin Austin Motoyama, R...
PAM
2009
Springer
13 years 11 months ago
Revisiting Route Caching: The World Should Be Flat
Internet routers’ forwarding tables (FIBs), which must be stored in expensive fast memory for high-speed packet forwarding, are growing quickly in size due to increased multihomi...
Changhoon Kim, Matthew Caesar, Alexandre Gerber, J...
SIGCOMM
2010
ACM
13 years 5 months ago
Rethinking iBGP routing
The Internet is organized as a collection of administrative domains, known as Autonomous Systems (ASes). These ASes interact through the Border Gateway Protocol (BGP) that allows ...
Iuniana M. Oprescu, Mickael Meulle, Steve Uhlig, C...
HPCA
2009
IEEE
14 years 5 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
IPPS
2007
IEEE
13 years 11 months ago
Table-lookup based Crossbar Arbitration for Minimal-Routed, 2D Mesh and Torus Networks
Crossbar arbitration—which determines the allocation of output ports to packets in the input queues—is a performance-critical stage in the overall performance of routers for i...
Daeho Seo, Mithuna Thottethodi