42 search results - page 8 / 9 » Heterogeneous Programmable Logic Block Architectures |
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
FPGA
2001
ACM
13 years 9 months ago
2001
ACM
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
ERSA
2008
13 years 6 months ago
2008
This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks...