7 search results - page 2 / 2 » Heuristics Versus Completeness for Graph Coloring |
CGO
2007
IEEE
14 years 3 days ago
2007
IEEE
Memory transfers are becoming more important to optimize, for both performance and power consumption. With this goal in mind, new register allocation schemes are developed, which ...
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
14 years 2 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...