43 search results - page 1 / 9 » Hiding Cache Miss Penalty Using Priority-based Execution for... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
HPCC
2009
Springer
13 years 9 months ago
2009
Springer
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
CF
2004
ACM
13 years 8 months ago
2004
ACM
Off-chip memory accesses are a major source of power consumption in embedded processors. In order to reduce the amount of traffic between the processor and the off-chip memory as ...
ISPASS
2009
IEEE
13 years 11 months ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...