43 search results - page 9 / 9 » Hiding Cache Miss Penalty Using Priority-based Execution for... |
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task ch...
ISCA
2000
IEEE
13 years 10 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
CODES
2009
IEEE
13 years 10 months ago
2009
IEEE
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...