12 search results - page 1 / 3 » Hiding Synchronization Delays in a GALS Processor Microarchi... |
ASYNC
2004
IEEE
13 years 8 months ago
2004
IEEE
We analyze an Alpha 21264-like Globally
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and Globally Asynchronous Locally Synchronous (G...
MICRO
2002
IEEE
13 years 9 months ago
2002
IEEE
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...