7 search results - page 2 / 2 » Hierarchical Error Diagnosis Targeting RTL Circuits |
DAC
1999
ACM
14 years 6 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
DT
2000
13 years 5 months ago
2000
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...