64 search results - page 3 / 13 » Hierarchical Optimization of Asynchronous Circuits |
ICRA
2009
IEEE
13 years 2 months ago
2009
IEEE
The design of a hierarchical planning system in which each level operates in parallel and communicates asynchronously is presented. It is shown that this Parallel Hierarchical Repl...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
IFIP
1992
Springer
13 years 8 months ago
1992
Springer
This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE