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ICCAD
1999
IEEE

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions

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Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions in the form "event a occurs before event b" can be used to remove redundant handshakes and associated logic. This paper presents a method for automatic generation of relative timing assumptions from the untimed specification. These assumptions can be used for area and delay optimization of the circuit. A set of relative timing constraints sufficient for the correct operation of the circuit is back-annotated to the designer. Experimental results for control circuits of a prototype iA32 instruction length decoding and steering unit called RAPPID ("Revolving Asynchronous Pentium R
Jordi Cortadella, Michael Kishinevsky, Steven M. B
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ICCAD
Authors Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens
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