249 search results - page 4 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
RSP
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
ASYNC
1997
IEEE
13 years 9 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
DATE
2009
IEEE
14 years 2 days ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
ASYNC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...