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» High Performance Array Processor for Video Decoding
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ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
13 years 9 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
DAC
2009
ACM
14 years 6 months ago
Decoding nanowire arrays fabricated with the multi-spacer patterning technique
Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS)...
M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De ...
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
14 years 2 months ago
Implementing Caches in a 3D Technology for High Performance Processors
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
Kiran Puttaswamy, Gabriel H. Loh
DAGSTUHL
2007
13 years 7 months ago
Energy Scalability and the RESUME Scalable Video Codec
In the context of the RESUME-project a scalable wavelet-based video decoder was built to demonstrate the benefits of reconfigurable hardware for scalable applications. Scalable v...
Harald Devos, Hendrik Eeckhaut, Mark Christiaens, ...
SPIESR
1996
118views Database» more  SPIESR 1996»
13 years 7 months ago
Performances of Multiprocessor Multidisk Architectures for Continuous Media Storage
Multimedia interfaces increase the need for large image databases, capable of storing and reading streams of data with strict synchronicity and isochronicity requirements. In orde...
Benoit A. Gennart, Vincent Messerli, Roger D. Hers...