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MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
13 years 10 months ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak
PRDC
2008
IEEE
13 years 11 months ago
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree ...
Viswanathan Subramanian, Arun K. Somani
SIGGRAPH
1994
ACM
13 years 9 months ago
IRIS performer: a high performance multiprocessing toolkit for real-time 3D graphics
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
John Rohlf, James Helman
VLSID
1993
IEEE
234views VLSI» more  VLSID 1993»
13 years 9 months ago
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V....
IPPS
2010
IEEE
13 years 2 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...