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ERSA
2006
197views Hardware» more  ERSA 2006»
13 years 6 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
ASAP
1996
IEEE
145views Hardware» more  ASAP 1996»
13 years 9 months ago
A Synthesis System For Bus-Based Wavefront Array Architectures
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
Reiner W. Hartenstein, Jürgen Becker, Michael...
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
13 years 9 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
CEEMAS
2007
Springer
13 years 11 months ago
Collaborative Attack Detection in High-Speed Networks
We present a multi-agent system designed to detect malicious traffic in high-speed networks. In order to match the performance requirements related to the traffic volume, the net...
Martin Rehák, Michal Pechoucek, Pavel Celed...
BMCBI
2005
100views more  BMCBI 2005»
13 years 4 months ago
Speeding disease gene discovery by sequence based candidate prioritization
Background: Regions of interest identified through genetic linkage studies regularly exceed 30 centimorgans in size and can contain hundreds of genes. Traditionally this number is...
Euan A. Adie, Richard R. Adams, Kathryn L. Evans, ...