Sciweavers

154 search results - page 31 / 31
» High level cache simulation for heterogeneous multiprocessor...
Sort
View
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 2 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
PPOPP
2003
ACM
13 years 10 months ago
Programming the FlexRAM parallel intelligent memory system
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able t...
Basilio B. Fraguela, Jose Renau, Paul Feautrier, D...
PPOPP
2003
ACM
13 years 10 months ago
Optimizing data aggregation for cluster-based internet services
Large-scale cluster-based Internet services often host partitioned datasets to provide incremental scalability. The aggregation of results produced from multiple partitions is a f...
Lingkun Chu, Hong Tang, Tao Yang, Kai Shen
TON
2012
11 years 7 months ago
A Transport Protocol to Exploit Multipath Diversity in Wireless Networks
Abstract—Wireless networks (including wireless mesh networks) provide opportunities for using multiple paths. Multihoming of hosts, possibly using different technologies and prov...
Vicky Sharma, Koushik Kar, K. K. Ramakrishnan, Shi...