116 search results - page 3 / 24 » High throughput architecture for packet classification using... |
DELTA
2008
IEEE
13 years 12 months ago
2008
IEEE
Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twis...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
SPAA
2009
ACM
2009
ACM
Field-split parallel architecture for high performance multi-match packet classification using FPGAs
13 years 10 months ago
ARC
2012
Springer
12 years 1 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
FPL
2006
Springer
13 years 9 months ago
2006
Springer
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...