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APCSAC
2001
IEEE
13 years 8 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
ECOOPW
1998
Springer
13 years 8 months ago
A Rational Approach to Portable High Performance: The Basic Linear Algebra Instruction Set (BLAIS) and the Fixed Algorithm Size
Abstract. We introduce a collection of high performance kernels for basic linear algebra. The kernels encapsulate small xed size computations in order to provide building blocks fo...
Jeremy G. Siek, Andrew Lumsdaine
IFE
2010
161views more  IFE 2010»
13 years 3 months ago
Adaptive estimation and prediction of power and performance in high performance computing
Power consumption has become an increasingly important constraint in high-performancecomputing systems, shifting the focus from peak performance towards improving power efficiency...
Reza Zamani, Ahmad Afsahi
DAC
2001
ACM
14 years 5 months ago
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...
BMCBI
2010
198views more  BMCBI 2010»
13 years 4 months ago
ClustalXeed: a GUI-based grid computation version for high performance and terabyte size multiple sequence alignment
Background: There is an increasing demand to assemble and align large-scale biological sequence data sets. The commonly used multiple sequence alignment programs are still limited...
Taeho Kim, Hyun Joo