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APCSAC
2001
IEEE

High-Performance Extendable Instruction Set Computing

9 years 1 days ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset and immediate operands can be extended to 32-bits via the operation of an extension flag. The code density of the EISC instruction set and its memory transfer performance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems. The compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations. This paper suggests a mechanism by which these dependencies might be removed in hardware.
Heui Lee, Paul Becket, Bill Appelbe
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where APCSAC
Authors Heui Lee, Paul Becket, Bill Appelbe
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