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» High-Radix Implementation of IEEE Floating-Point Addition
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ARITH
2005
IEEE
13 years 11 months ago
High-Radix Implementation of IEEE Floating-Point Addition
We are proposing a micro-architecture for highperformance IEEE floating-point addition that is based on a (non-redundant)high-radix representation of the floatingpoint operands....
Peter-Michael Seidel
ARITH
1999
IEEE
13 years 9 months ago
Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms
This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with...
David Lewis
ARITH
2007
IEEE
13 years 9 months ago
A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [1] was revised [2], and an important addition is the definition of decimal floating-point arithmetic. This is inte...
Marius Cornea, Cristina Anderson, John Harrison, P...
ARITH
1999
IEEE
13 years 9 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
ISLPED
1997
ACM
106views Hardware» more  ISLPED 1997»
13 years 8 months ago
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Kha...