Sciweavers

54 search results - page 9 / 11
» High-level synthesis scheduling and allocation using genetic...
Sort
View
INFOCOM
2003
IEEE
13 years 11 months ago
Distributed Queueing in Scalable High Performance Routers
—This paper presents and evaluates distributed queueing algorithms for regulating the flow of traffic through large, high performance routers. Distributed queueing has a similar ...
Prashanth Pappu, Jyoti Parwatikar, Jonathan S. Tur...
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
13 years 11 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 10 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
EGH
2005
Springer
13 years 11 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
SIMULATION
1998
177views more  SIMULATION 1998»
13 years 5 months ago
Simulation and Planning of an Intermodal Container Terminal
A decision support system for the management of an intermodal container terminal is presented. Among the problems to be solved, there are the spatial allocation of containers on t...
Luca Maria Gambardella, Andrea Emilio Rizzoli, Mar...