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266views
12 years 10 months ago
NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
C. Farabet, B. Martini, B. Corda, P. Akselrod, E. ...
ISCAS
2005
IEEE
182views Hardware» more  ISCAS 2005»
13 years 11 months ago
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems
– The trend in communication systems is towards more rapidly changing specifications with shorter time intervals between updates of existing standards. This results in a coexiste...
Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed
VLSISP
2011
358views Database» more  VLSISP 2011»
13 years 10 days ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
CDES
2006
184views Hardware» more  CDES 2006»
13 years 6 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
13 years 10 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...