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ICASSP
2011
IEEE
12 years 8 months ago
High-throughput implementation of tree-search algorithms for vector precoding
This contribution analyzes the architecture design and FPGA implementation of high-throughput multiuser vector precoders. The most complex task of such precoders, i.e. the search ...
Maitane Barrenechea, Luis G. Barbero, Idoia Jimene...
ISCAS
2007
IEEE
93views Hardware» more  ISCAS 2007»
13 years 11 months ago
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding
Abstract— This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme...
Andreas Burg, Dominik Seethaler, Gerald Matz
FPGA
2005
ACM
121views FPGA» more  FPGA 2005»
13 years 10 months ago
Floating-point sparse matrix-vector multiply for FPGAs
Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not...
Michael DeLorimier, André DeHon
BMCBI
2007
226views more  BMCBI 2007»
13 years 5 months ago
MiRFinder: an improved approach and software implementation for genome-wide fast microRNA precursor scans
Background: MicroRNAs (miRNAs) are recognized as one of the most important families of noncoding RNAs that serve as important sequence-specific post-transcriptional regulators of ...
Ting-Hua Huang, Bin Fan, Max F. Rothschild, Zhi-Li...
FPGA
2009
ACM
273views FPGA» more  FPGA 2009»
13 years 11 months ago
A parallel/vectorized double-precision exponential core to accelerate computational science applications
Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e−x in computer simulation experiments. While it is common to ...
Robin Pottathuparambil, Ron Sass