Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a f...
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nass...
— This paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. The additional force which distrib...
In this paper, a novel thermal-aware dynamic placement planner for reconfigurable systems is presented, which targets transient temperature reduction. Rather than solving time-...
Shahin Golshan, Eli Bozorgzadeh, Benjamin Carri&oa...
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Luka...