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CDES
2006
101views Hardware» more  CDES 2006»
13 years 6 months ago
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
HPCA
2006
IEEE
14 years 5 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ASPLOS
2004
ACM
13 years 10 months ago
Fingerprinting: bounding soft-error detection latency and bandwidth
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection techniqu...
Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Baba...
HPCA
2008
IEEE
13 years 11 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ICCAD
2010
IEEE
186views Hardware» more  ICCAD 2010»
13 years 2 months ago
Application-Aware diagnosis of runtime hardware faults
Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Currently available online t...
Andrea Pellegrini, Valeria Bertacco