59 search results - page 3 / 12 » ILP Models for the Synthesis of Asynchronous Control Circuit... |
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...
ACSD
2009
IEEE
13 years 3 months ago
2009
IEEE
This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
VLSI
2005
Springer
13 years 11 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
ACSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...