11 search results - page 1 / 3 » IP Watermarking Using Incremental Technology Mapping at Logi... |
TCAD
2008
13 years 4 months ago
2008
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
ICCAD
1998
IEEE
13 years 8 months ago
1998
IEEE
The intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propo...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
We propose a logic synthesis flow which utilizes the functionality of circuit to synthesize a domino-cell network which will have more wires crosstalk-immune to each other. For t...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...