155 search results - page 30 / 31 » ITOP: integrating timing optimization within placement |
FPGA
2010
ACM
14 years 2 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
ICCV
2007
IEEE
13 years 7 months ago
2007
IEEE
Our goal is to create a visual odometry system for robots and wearable systems such that localization accuracies of centimeters can be obtained for hundreds of meters of distance ...
SSDBM
2010
IEEE
13 years 3 months ago
2010
IEEE
Graphs are prevailingly used in many applications to model complex data structures. In this paper, we study the problem of supergraph containment search. To avoid the NP-complete s...
SIGMETRICS
2012
ACM
11 years 8 months ago
2012
ACM
The demand for data center computing increased significantly in recent years resulting in huge energy consumption. Data centers typically comprise three main subsystems: IT equip...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...