2 search results - page 1 / 1 » Identification of unsettable flip-flops for partial scan and... |
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...