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IEICET
2008
57views more  IEICET 2008»
13 years 5 months ago
Impact of Well Edge Proximity Effect on Timing
This paper studies impact of the well edge proximity effect on digital circuit delay, based on model parameters extracted from test structures in an industrial 65nm wafer process. ...
Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsum...
FCCM
2007
IEEE
137views VLSI» more  FCCM 2007»
14 years 3 days ago
Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array
— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. This p...
I. Faik Baskaya, Brian Gestner, Christopher M. Twi...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
13 years 11 months ago
Stochastic Power Grid Analysis Considering Process Variations
In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid’s...
Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Pa...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
13 years 11 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
DAC
2007
ACM
14 years 6 months ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan