479 search results - page 1 / 96 » Implementation and Evaluation of On-Chip Network Architectur... |
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
ISVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, we discuss the possibility of achieving onchip fault-tolerant communication based on a new communication paradigm called stochastic communication. Specifically, for...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a novel architecture for on-chip neural network training using particle swarm optimization (PSO). PSO is an evolutionary optimization algorithm with a growing ...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...