80 search results - page 1 / 16 » Implementation and Evaluation of a Dynamically Routed Proces... |
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
NCA
2007
IEEE
13 years 11 months ago
2007
IEEE
The assessment of routing protocols for wireless networks is a difficult task, because of the networks’ highly dynamic behavior and the absence of benchmarks. However, some of ...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...