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» Implementing Performance Competitive Logical Recovery
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ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 2 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
SGAI
2009
Springer
13 years 10 months ago
Improving Cooperative PSO using Fuzzy Logic
PSO is a population-based technique for optimization, which simulates the social behavior of the fish schooling or bird flocking. Two significant weaknesses of this method are: fir...
Zahra Afsahi, Mohammad Reza Meybodi
SIGCOMM
2004
ACM
13 years 11 months ago
The design and implementation of a next generation name service for the internet
Name services are critical for mapping logical resource names to physical resources in large-scale distributed systems. The Domain Name System (DNS) used on the Internet, however,...
Venugopalan Ramasubramanian, Emin Gün Sirer
CORR
2006
Springer
135views Education» more  CORR 2006»
13 years 5 months ago
Constraint Functional Logic Programming over Finite Domains
In this paper, we present our proposal to Constraint Functional Logic Programming over Finite Domains (CFLP(FD) ) with a lazy functional logic programming language which seamlessl...
Antonio J. Fernández, Maria Teresa Hortal&a...
ICCAD
1999
IEEE
119views Hardware» more  ICCAD 1999»
13 years 9 months ago
Factoring logic functions using graph partitioning
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
Martin Charles Golumbic, Aviad Mintz