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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 11 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
13 years 10 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
DAC
2006
ACM
14 years 6 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
ICCAD
2010
IEEE
109views Hardware» more  ICCAD 2010»
13 years 3 months ago
Misleading energy and performance claims in sub/near threshold digital systems
Abstract-- Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper i...
Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Ma...
JNW
2006
126views more  JNW 2006»
13 years 5 months ago
Gateway Deployment optimization in Cellular Wi-Fi Mesh Networks
With the standardization of IEEE 802.11, there has been an explosive growth of wireless local area networks (WLAN). Recently, this cost effective technology is being developed aggr...
Rajesh Prasad, Hongyi Wu