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VLSID
1999
IEEE
100views VLSI» more  VLSID 1999»
13 years 8 months ago
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
Andrew B. Kahng, Sudhakar Muddu
ISPD
1998
ACM
99views Hardware» more  ISPD 1998»
13 years 8 months ago
New efficient algorithms for computing effective capacitance
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
Andrew B. Kahng, Sudhakar Muddu
DAC
1999
ACM
13 years 8 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
LCR
1998
Springer
150views System Software» more  LCR 1998»
13 years 8 months ago
Improving Locality in Out-of-Core Computations Using Data Layout Transformations
Programs accessing disk-resident arrays, called out-of-core programs, perform poorly in general due to an excessive number of I/O calls and insufficient help from compilers. In ord...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
CCGRID
2011
IEEE
12 years 8 months ago
A Segment-Level Adaptive Data Layout Scheme for Improved Load Balance in Parallel File Systems
Abstract—Parallel file systems are designed to mask the everincreasing gap between CPU and disk speeds via parallel I/O processing. While they have become an indispensable compo...
Huaiming Song, Yanlong Yin, Xian-He Sun, Rajeev Th...